Fig. 20.8. Cross-sectional view of field effect transistor (FET) structures: (a) the terminal designations and biasing conditions for conventional Si-based MOSFETs [20.48]. G, D, B, and S, respectively, denote the ground, drain, base, and source, (b) The corresponding structure for the fullerene (C60) FET device [20.49].
etry the source (S) and base (B) are grounded. As the gate voltage VG is increased VG > VT, where VT is the depletion-inversion transition-point voltage, an inversion layer containing mobile carriers is formed adjacent to the Si surface, creating a source-to-drain channel. Now, by keeping VG fixed and varying VD, the current-voltage characteristic ID vs. VD of the transistor can be determined for various gate voltages.
Fullerene-based «-channel FETs have been constructed [20.49-52] and an example of such a device is shown in Fig. 20.8(b). The corresponding current-voltage characteristics for this fullerene FET are shown in Fig. 20.9. In the fullerene FET shown in Fig. 20.8(b), a highly doped n-type silicon wafer takes the place of the gate metal, a ~30-300 nm thick layer of Si02 serves as the oxide, and the fullerene film is the semiconductor. When an appropriate positive gate voltage VG is applied (see Fig. 20.9), the drain current ID increases, which indicates that a conduction channel is formed near the fullerene-insulator interface. The sign of the response indicates b
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