Microfabrication

Most commercial microcantilevers and nanocantilevers focus on silicon or silicon nitride cantilevers due to their availability and easy integration with silicon-based technology (Lavrik et al. 2004).

13.6.1 Si-based Cantilever

Typically, fabrication of suspended microstructures, such as a cantilever transducer, consists of deposition, patterning, and etching steps that define, respectively, thickness, lateral sizes, and the surrounding of the cantilever. One of the frequently used approaches in microcantilever fabrication involves deposition of a sacrificial layer on a prepatterned substrate followed by deposition of a structural material layer (such as a silicon nitride layer or a polysilicon layer) using LPCVD or PECVD processes. By varying the conditions of these deposition processes, the stress and stress gradient in the deposited layers can be minimised so that suspended structures do not exhibit significant deformation after they are released by etching of the sacrificial layer. The cantilever shapes can be defined by patterning the silicon nitride film on the top surface using photolithography followed by reactive ion etching (RIE). Photolithographic patterning of the structural material (silicon nitride or polysilicon) on the bottom surface is used to define the mask for an anisotropic bulk etch of Si. The silicon substrate is then etched away to produce free-standing cantilevers.

Fig. 13.1. Illustration of the steps in a process flow used for fabrication of silicon nitride cantilevers. The process involves a deposition of a structural silicon nitride layer on a silicon wafer with a prepatterned sacrificial layer. The cantilever shapes can be defined by patterning the silicon nitride film on the top surface using photolithography followed by reactive RIE (Lavrik et al. 2004)

Fig. 13.1. Illustration of the steps in a process flow used for fabrication of silicon nitride cantilevers. The process involves a deposition of a structural silicon nitride layer on a silicon wafer with a prepatterned sacrificial layer. The cantilever shapes can be defined by patterning the silicon nitride film on the top surface using photolithography followed by reactive RIE (Lavrik et al. 2004)

Using a similar sequence of processes, single-crystal silicon cantilevers can be created with the difference that doping of silicon or epitaxy of a doped silicon layer substitutes deposition of a silicon nitride layer.In order to avoid any bulk micromachining, such as through-etch of silicon in KOH, various cantilever fabrication processes based on the use of a sacrificial layer were developed. These processes frequently rely on silicon oxide as a material for the sacrificial layer. The use of a sacrificial layer for fabrication of silicon nitride microcantilever is illustrated in Fig. 13.1. While the use of a sacrificial layer introduces additional restrictions on the material choice, it enables process flows that are fully compatible with standard complementary-metal-oxidesemiconductor (CMOS) chip technology. These silicon-based nanomechanical cantilevers mainly rely on the cantilever bending that comes from surface stress when the target DNA or protein molecules are specifically bound to their receptors that are immobilised on the surface of the cantilever. However, silicon-based nanomechanical cantilevers require an expensive optical apparatus because they cannot acquire a direct electrical signal. In addition, there are generally optical limitations such as a narrow dynamic range and parasitic deflection in optical measurements.

13.6.2 Piezoresistive Integrated Cantilever

A full Wheatstone bridge was symmetrically placed on a chip, with two resistors on the cantilevers and two resistors on the substrate. One cantilever can be used as the reference cantilever and the other can be used for the measurement. The materials used to fabricate cantilevers are single-crystal silicon, amorphous silicon, and microcrystalline silicon. The starting materials of the single-crystal silicon cantilevers is silicon-on-insulator wafers with a 220 nm silicon membrane after thinning down the top silicon layer, and a 400 nm silicon dioxide intermediate layer. Fig. 13.2 shows SEM photographs of piezoresistive sensor arrays and a schematic cross section. Amorphous silicon (580°C) and microcrystalline silicon (610°C) cantilevers were fabricated from 55 nm of silicon nitride with LPCVD on silicon wafers. Next, 150 nm of amorphous silicon and microcrystalline silicon layers were separately deposited with LPCVD. The wafers were divided into two groups for boron-ion implantation at 30 keV with a dose of

53 x 10 cm- or 53 x 10 cm- for single-crystal silicon and 53 x 10 cm- or 53 x 1015 cm-2 for amorphous and microcrystalline silicon layers. The piezoresistors were patterned and then defined using SF6 RIE. The contact pad and the cross beam of all the wafers were implanted with 53 x 1015 cm-2 boron ion, and a mask was used to preclude the resistance of the cross beam and to form a good electrical contact with metal. Subsequently, 280 nm of silicon nitride was deposited as a protective layer and as an etch mask for the later wet etching. The doped boron was activated at 950°C for 10 min or 1050°C for 30 min. The cantilevers were defined from the front. The silicon nitride was etched with RIE, and then the cantilevers were released by KOH front-side etching. The channel thickness had been controlled to be about 50 mm. Contact holes were opened with the help of LPCVD SiO2. Finally, 20/500 nm Ti/Al metal wiring film for the piezoresistor was made by e-beam evaporation.

Was this article helpful?

0 0
Brain Blaster

Brain Blaster

Have you ever been envious of people who seem to have no end of clever ideas, who are able to think quickly in any situation, or who seem to have flawless memories? Could it be that they're just born smarter or quicker than the rest of us? Or are there some secrets that they might know that we don't?

Get My Free Ebook


Post a comment