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n be knocked out or sputtered away easily from the two or three atomic layers of the work surface. However, when the ion incidence angle further increases, the machining rate begins to decrease because the ion current density for unit working area decreases by cosO and the number of ions reflected from the surface of the workpiece without sputtering off atoms increases. Success of ion beam polishing depends crucially on the grain size and initial morphology of the work surface. With very small grain size, the machining rate of each grain will be almost the same, and therefore uniform machining over the surface will take place. For large grain size, the difference between the machining rates of the grains results in the increase in value of surface roughness (Miyamoto 1993). Ion beam machining is an ideal process for nano-finishing of high melting point and hard brittle materials such as ceramics, semiconductors, diamonds etc. As there is no mechanical load on the workpiece while finishing, it is suitable for finishing of very thin objects, optics and soft materials such as CaF2. Diamond styli for profilometer were sharpened using Kaufman type ion source. Argon ion beam of energy E=10keV and ion current density of 0.5 mA/cm2 was used to sharpen the styli to the tip radius of 10 nm (Miyamoto and Ezawa 1991).

8.3.8 Chemical Mechanical Polishing (CMP)

Chemical Mechanical Polishing (CMP) is the fastest growing process technology in the semiconductor manufacturing. CMP is a planarisation process, which involves a combination of chemical and mechanical actions. The importance of each contribution depends on the polished material. It was developed at IBM in the mid-1980s as an enabling technology to planarise SiO2 interlevel dielectric (ILD) layers so that three or more levels of metal could be integrated into a high-density interconnect process. This technology was adapted from silicon wafer polishing. By employing CMP, subsequent structures could he fabricated on a nearly planar surface. The initial application of CMP was ILD planarisation, but its application to other areas in the overall semiconductor fabrication sequence followed quickly.

A similar variant is Chemo-Mechanical polishing in which driving factor for material removal is chemical action between abrasive particles and workmaterial followed by mechanical action for the removal of reaction products (Vora et al. 1982). In chemical mechanical polishing, the reaction is between the fluid and the workmaterial, and the abrasive removes the reaction product by mechanical action (Nanz and Camilletti 1995). Chemo-mechanical polishing is expected to overcome many problems of surface damage associated with hard abrasives, including pitting due to brittle fracture, dislodgement of grains, scratching due to abrasion, etc. , resulting in smooth, damage free surfaces (Komanduri et al. 1997). A schematic of CMP planarisation process is shown in Fig. 8.21. The wafers are pressed downward by carriers and rotated against the polishing pad covered with a layer of silica slurry.

The polishing pad on rotating plate is used to hold the slurry particles, transmit load to the particle-wafer interface, and conform precisely to the wafer being polished. Aqueous colloidal silica suspension is widely used for polishing. Initial chemical reaction of silicon with the aqueous solution form a thin silica layer and this is then mechanically removed by the polishing slurry. The thin layer of silica reduces the friction force, provides uniform distribution of slurry particles and remove eroded material and heat generated. During CMP, the kinetic energy of the slurry particles moving between the wafer and the pad, erodes the surface of the wafer. CMP has been used for a long time in manufacturing of silicon wafers. CMP results in defect free surfaces in contrast to mechanically polished surfaces (Jhansson et al. 1989). Simultaneous double side polishing is also feasible (Wenski et al. 2002). Double side polishing gives a better parallelism compared to single side polishing and less adherence of particles since both sides are smooth. Another use of CMP substrate is in thin film transistor (TFT) technology (Chang et. al 1996) and polishing of IC wafers (Venkatesh et al. 2004). In TFT, used for instance for making flat displays, polycrystalline silicon is deposited on glass substrates. To obtain more global planarisation in contrast to local, CMP was introduced to planarise the deposited interlevel dielectric (ILD) oxide layers in metal interconnection layers. CMP for ILD planarisation is used in the aluminum wiring - tungsten plug interconnection technology.

Fig. 8.21. Schematic of CMP planarisation process equipment (Hayashi et al.)

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