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Figure 11. (a) Optical image of the capacitor arrays, the minimum diameter or size is 50 ¡m. (b) 2D profile (c) SEM image of layers of 45-nm silica particle thin film. (d) 3D plot of the capacitors. Reprinted with permission from [203], F. Hua et al., Nanotechnology 14, 453 (2003). © 2003, Institute of Physics.

Figure 11. (a) Optical image of the capacitor arrays, the minimum diameter or size is 50 ¡m. (b) 2D profile (c) SEM image of layers of 45-nm silica particle thin film. (d) 3D plot of the capacitors. Reprinted with permission from [203], F. Hua et al., Nanotechnology 14, 453 (2003). © 2003, Institute of Physics.

monolayer was formed. It shows that at the sixth cycle, the thickness of the SiO2 layers is 260 nm. When added to the 300 nm aluminum electrode, the height of the whole device is 567 nm, well in compliance with the 2D profile of Figure 11(b).

The fabricated device demonstrates the C-V curve of a typical MOS capacitor with distinct accumulation, depletion, and inversion regions, as shown in Figure 12. The MOS structure is basically a capacitor with the silica as the dielectric material. If the silicon were a perfect conductor, the parallel-plate capacitance would be determined by the oxide capacitance as it is in the accumulation region. However, it always deviates from the oxide capacitance due to the voltage dependence of the surface space-charge layer in silicon. The space-charge occurring at the interface of silicon and oxide acts as another capacitance in a series with the oxide capacitor, giving an overall capacitance that is smaller than the pure oxide capacitance. Since the inversion of a P-type MOS capacitor happens at a positive voltage and an N-type one at a negative voltage, the C-V curves move in opposite directions for P- and N-type MOS capacitors. If the layer of silicon dioxide was produced by conventional thermal oxidation, the dielectric constant would be 3.9. Given the size of each square device, 200 ¡m by 200 ¡m and 267 nm high, the oxide capacitance is calculated as 5.2 pF, reasonably close to the experimental data, 8 pF. The slightly larger value means a larger dielectric constant of the LbL, self-assembled insulator layer. The precursor and intermediate polyion multilayer is the root for the higher dielectric constant because the dielectric constant of the polyion film is normally 10 times higher than silica [204]. The experimental results also show that the capacitance of each device is strictly proportional to the area of the electrode, implying an extremely high reproducibility of the processes.

In our process, a conventional lithographic technique, such as lift-off, was used to pattern the capacitors on multilayer films. However, because the LbL-self-assembled nanoparticle films are unlike the conventional thin films in

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