Lithographic Approach To Pattern Layerbylayer Thin Films

Nanoassembly of ultra-thin films through alternate adsorption of oppositely charged components (linear polyions, nanoparticles, and enzymes) allows the formation of layers with component location precision of a few nanometers in the direction perpendicular to the surface. Since its demonstration by Decher et al. [180, 181], applications have been found in electro-optical devices, biocompatible coverage, and in bioreactors [180-186]. The typical procedure of layer-by-layer self-assembly is as follows: A pretreated silicon substrate is immersed in a cationic solution for 10 min, forming a single layer of cationic polyelectrolytes on the substrate. The substrate is then rinsed. Next, it is immersed in a polyanion solution for 10 min to adsorb a layer of anionic polyelectrolyte. The process can be repeated indefinitely; the only condition is a proper alternation of positive and negative components. Linear polyions frequently used in the layer-by-layer (LbL) assembly are cationic poly(ethylenimine) (PEI), PDDA, PAH, polylysine, chitosan, and anionic sodium PSS, and poly(vinylsulfate), polyacrylic acid, and DNA. Enzymes and charged nanoparticles were also used in the LbL assembly [179]. To use LbL multilayers in devices, one has to provide film ordering not only in a vertical direction but also in the planar direction. This is critical for nanodevice production, such as nanoelectronic chips or nano electro mechanical systems (NEMS) [192-195].

There are works on applications of the layer-by-layer assembly on two-dimensional (2D) patterns [196-201]. They are based mostly on the microprinting of thiol compounds on gold and further assembly of the polyion multilayers on charged patterns, and they were developed by Hammond et al. [196-199]. This strategy is designed to produce patterns by stamping onto substrate chemicals with different functionalities, that is, polyion adhesive or resisting. The polyions were directed only to charge "attractive" regions and were repelled from the resistant regions. Whitesides et al. [200] crystallized latex particles in capillary channels produced by PDMS micromolding and made 3D ensembles of 450-nm spheres with a resolution of ca.1 /m. In another approach [201], poly(pyrrole) and poly(styrenesulfonate) were LbL-assembled on the 2D charged micropattern produced on a fluoropolymer by plasma treatment. The three methods described were quite successful, but restricted in applications by substrate materials (gold, fluoropolymers) or by the necessity of special plastic stamps. We presented two approaches to realize 2D patterning of self-assembled multilayers by silicon-based lithographical technology, which is a well-established industrial process.

The first one is referred to as the metal mask approach. By using this method, we avoid the selective deposition, which demands strict control and consequently obtains extremely high reproducibility and a simplified process. Since layer-by-layer self-assembly and lithography techniques are mature processes, and lithography is widely applied to the modern semiconductor industry, a combinative technique will be economic and suitable for mass production. By just following the traditional process, the nanostructures comprised of nano-building bricks can be realized. As it behaves in the semiconductor industry, the process results in such a high reproducibility that distinct patterns (in this experiment, 10 /m) can be created in almost all the dyes on the wafer. Commercial electronic and photonic devices, such as metal-oxide semiconductor FET (MOSFET) or solar cells with nanostructures, are expected to be fabricated by this method at a considerably lower cost and temperature. Layer-by-layer self-assembly was employed to deposit the nanoparticle-based thin film on a substrate while using a semiconductor process to pattern the thin film [202]. At first, a layer of nanoparticles is adsorbed onto a silicon wafer. Then a layer of aluminum and resist are deposited and coated on top of the nanoparticle layer. Patterns are made on resist by UV lithography and transferred to a aluminum layer by etching aluminum. As a result, nanoparticles previously covered under aluminum begin to be open to the air. Then, it is etched by oxygen plasma, and nanoparticles are removed in compliance with the designed patterns. During the etching process, metal acts as the mask over the nanoparticles. After the remaining aluminum and resist are dissolved, only the desired pattern is left on the substrate.

The second patterning approach is called a "lift-off" since lift-off acts as a critical step in the process. At the beginning, photoresist is spinned on a silicon wafer and patterned. Then nanoparticles are deposited with layer-by-layer assembly on the whole wafer. Eventually, the wafer is put into acetone solution to dissolve resist and particles self-assembled on it are removed as well [202].

Both methods work well for the thin film patterning. As for the lift-off method, it can be applied to all types of nanoparticles. In the other experiments, the metal mask method succeeded in controlling the spatial position of organic polystyrene particle by oxygen plasma etching. As a matter of fact, it can also be applied to inorganic particles if the appropriate recipe is available. If not, the flexibility of the mature semiconductor process can provide a simple wet etching to deal with it as a substitute to the dry etching.

Both methods can be applied to 3D fabrication as well as functional devices. In the 3D case, some factors have to be seriously controlled such as height, surface or border roughness, and sidewall profile. Two methods can work out a 3D structure individually or both of them can be used if necessary. Table 1 shows the comparison of two methods.

In our experiment, the capacitor arrays were patterned by the "modified lift-off" as illustrated in Figure 9. These capacitors can be fabricated onto integrated circuit chips. Metal-oxide semiconductor (MOS) capacitors, with thermal SiO2 as the gate oxide, have become the prime structure to carry out digital functions in silicon-integrated circuits. However, the fabrication of a MOS capacitor, using the conventional silicon MOS technology, demands sophisticated facilities. High process temperature also needs to be balanced to avoid the damage to subsequent processes, and the growth rate of the thermal silicon dioxide is usually very low. Hereby, an approach to fabricate the basic MOS capacitor with a technique combining traditional lithographic technique and LbL self-assembly was developed because the dielectric layer consisting of silica and polyion can be self-assembled easily and rapidly. The insulating layer is made up of six layers of LbL, self-assembled silica nanoparticle thin

Table 1. Comparison of lift-off and metal mask methods.
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