Float zone FZ crystal growth

If high purity or oxygen-free silicon is needed, float zone (FZ) crystal growth is used. In the FZ-method, a polysilicon ingot is placed on top of a single-crystal seed. The polycrystalline ingot is heated externally by an RF coil, which locally melts the ingot. The coil and the melted zone move upwards, and a single crystal solidifies on top of the seed crystal.

The highest FZ-silicon resistivities are of the order of 20 000 ohm-cm, compared to 100 to 1000 ohm-cm for CZ. Because there is no silica crucible, there is no oxygen, and metal contamination from the crucible is also eliminated. FZ wafers, however, are mechanically weaker than CZ-wafers because oxygen mechanically strengthens silicon. FZ wafers are available only in smaller diameters, 150 mm maximum, with a 200 mm FZ demonstrated but not used in device manufacturing. When doped FZ-silicon is made, dopants are introduced by flushing the melt zone with gaseous dopants such as phosphine (PH3) or diborane (B2H6). High resistivity FZ is often doped via neutron transmutation doping (NTD)

according to Equation (4.6)

A silicon nucleus captures a neutron, and the newly formed nucleus decays by p-decay. This doping method explains why high resistivity silicon (5 -20 kohm-cm) is available in n-type.


Silicon has a cubic diamond lattice structure (Figure 4.3). The unit cell can be thought of as two interleaved face centred cubic (FCC) lattices with their origins in (0, 0, 0) an d (1/4, 1/4, 1/4). The distance between two atoms is V3/4a, and radius *j3/8a, where a is the unit cell edge length, 5.43095 A. As shown in Figure 4.3, there are 18 atoms to be considered: 8 at vertices (they are shared between 8 unit cells, and therefore contribute one atom to each unit cell; 6 face atoms are shared between two neighbouring unit cells, and contribute 3 atoms and there are four atoms fully inside the unit cell. The volume fraction of the space filled by silicon atoms is 34%, very low compared to hexagonal close packing, which fills 74% of the space. This open structure of silicon is important for diffusion.

Miller indices define the planes of a crystal. The plane that defines the faces of the cube (see Figure 4.4) intersects axes 1, 2, 3 at (1, to, to), respectively. The Miller index of a plane is given by the reciprocal of these intersects, that is, (1, 0, 0). The edges that tie planes are designated (1, 1, 0) and the diagonal planes are (1, 1, 1). The crystal structure is of course always the same, but it looks different when viewed from different directions: (100) corresponds to front view; (110) to edge view and (111) to vertex view (Figure 4.5). The set of six equivalent planes (the six faces of the cube) together

Float Zone For Crystal Growth Silicon
Figure 4.3 Silicon lattice: the unit cell consists of 8 atoms. Reproduced from Jenkins, T. (1995), by permission of Prentice Hall
Crystal Planes Silicon
Figure 4.4 Some important silicon crystal planes with their Miller indices
Miller Indices Silicon

are designated {100}. There are 12 (1, 1, 0) and 8 (1, 1, 1) planes. Wafers are sometimes cut to other index planes, most notably (311) and (511).

Fourfold symmetry of (100) and sixfold symmetry of (110) and (111) can be seen in Figure 4.5, and it will become apparent in anisotropic wet etching of silicon (to be discussed in Chapter 21).

The angles between the planes can be calculated from the scalar product of the normal vectors a • b = |a||b| cos(a, b) (4.7)

Visual examination shows that (100) and (110) planes meet at 45° and all the other angles can be calculated easily, when the negative unit vectors are accounted for: 110 is (—1, 1, 0). The angle between (111) and (100) planes is calculated from 1 = V3 cos a, giving a = 54.7°.

In order to get familiar with the silicon crystal structure, the paper fold model shown in Figure 4.6 becomes handy. Copying the model on an overhead transparency and gluing it together will result in a 26-gon, which visualizes the crystal planes nicely. It will be indispensable when crystal-plane dependent etching of silicon will be discussed in Chapters 21 and 28.

Wafers of two crystal orientations are widely used in microfabrication: <100> and <111>. The former is the main material for CMOS and bulk microme-chanics; the latter for bipolar transistors, power semiconductor devices and radiation detectors that rely on epitaxial deposition.


As listed in Table 4.3, silicon ingots are transformed into wafers by a long process which includes mechanical, thermal and chemical treatments and many cleaning and inspection steps.

The silicon-crystal orientation is determined by the seed crystal. After the ingot has cooled down, it is cut to ca. 50 cm stocks, which are measured for crystal orientation by X-ray diffraction. A flat or a notch is

Silicon 110 Wafer Secondary Flat

Figure 4.6 Fold-up paper model of silicon crystal planes. (This figure can be copied from Appendix B.) Fold model courtesy of Hiroshi Toshiyoshi, University of Tokyo

Table 4.3 Silicon wafering process

• Ingot crystal orientation by XRD

• Flat grinding

• Sawing ingot into wafers

• Edge smoothing

• Laser scribing

• Annealing to destroy thermal donors

• Final polishing

• Inspections then ground into the ingot to establish orientation. The flat or notch of a <100> wafer is oriented along the [110] direction (Figure 4.7).

The ingot is then sawed to slices. The surface of a <100> wafer is a (100) plane with [100] surface normal vector, usually cut as precisely as practical. < 111> wafers are often miscut a few degrees because of epitaxial deposition considerations.

Flat and notches are used by automatic wafer handlers to orient wafers inside the equipment, and devices can be oriented relative to the crystal planes. This latter aspect is especially important in micromechanics in which crystal-plane-dependent anisotropic etching is a major technique. Secondary flats are used to identify the doping type and the orientation of wafers (Figure 4.8).

Silicon Wafer 100 Plane
the (100) planes defines the wafer surface, the vector normal to the surface is in the direction [100] and the flat is along direction [110]

The next step is lapping: waviness and taper from the sawing are removed by lapping. In lapping, the wafers are rotating between two massive steel plates with alumina slurry. Lapping ensures not only parallelism of wafer surfaces but also equal damage depth. Surface roughness is ca. 0.1 to 0.3 ^m after the lapping step. The edges of the wafers are then bevelled in order to prevent the chipping of silicon during wafer handling and to eliminate watermarks during the drying steps.

(111) p-type (111) n-type (100) p-type (100) n-type (100) n-type Figure 4.8 Wafer flats and notches for identifying wafer orientation and doping type

(111) p-type (111) n-type (100) p-type (100) n-type (100) n-type Figure 4.8 Wafer flats and notches for identifying wafer orientation and doping type

Wafer breakage often starts from a crack at the wafer edge, and because silicon is brittle, the crack propagates through the whole wafer. The wafers are marked by laser scribing. This is done early on so that subsequent steps remove the silicon dust generated by marking. Alphanumeric or bar-code marking enable wafer identity tracking during the processing.

Etching is then used to remove the lapping damage: both alkaline (KOH) and acidic (HF-HNO3) etches can be used. Roughness is reduced somewhat in acid etching, but not in alkaline etching. An annealing step at 600 to 800 °C destroys thermal donors that are charged interstitial oxygen complexes.

Final polishing with 10 nm silica slurry in alkaline solution removes ca. 20 ^m of silicon and results in 0.1 to 0.2 nm RMS surface roughness. Silicon is lost in the above-mentioned steps so that ca. half of the original ingot ends up as wafer material. In many power-device and solar-cell applications polishing is not needed because the structures are wide and films are rather thick, therefore, the etched wafer surface quality is enough. This is a significant cost-saving because polishing is an expensive step. On the other hand, in many micro-electro-mechanical system (MEMS) applications, double-side polishing is essential both for double-side lithography and for wafer bonding.

Inspection and cleaning steps constitute a major fraction of all wafering steps. The wafers are measured for mechanical and electric properties. Contact-less measurements, for example, capacitance, optical and eddy-current methods, are preferred because contact methods introduce contamination and damage. Wafers are specified for particle cleanliness. Laser light scattering can be used to measure particle size distributions down to 60 nm sizes, but even unaided eye can detect particles larger than ca. 0.3 ^m because of their scattering under intense light (e.g., from a slide projector).

Wafers are specified for a number of electrical, mechanical, contamination and other properties as agreed between the wafer manufacturer and chip maker. The specifications in Table 4.4 shows examples of wafer specifications, both for integrated circuits and microelectrical systems. Wafer resistivities and dopant concentrations, and the corresponding short-hand notations are shown in Table 4.5. More discussion on wafer specs will be found in Chapters 24 and 25.

Table 4.4 Specifications for 100 mm wafers, some typical values



Growth method










0.0 ± 1.0°

0.0 ± 0.2°


16-24 ohm-cm

1 -10 ohm-cm


100.0 ± 0.5 mm

100.0 ± 0.5 mm


525 ± 25 ^m

380 ± 10 ^m

Front side






Primary flat

<110> ± 1 deg,


32.5 ± 2.5 mm

Oxygen level

13-16 ppma

11-15 ppma


<20 @ 0.3 ^m

<20 @ 0.3 ^m

Table 4.5 Resistivity versus dopant concentration

Dopant level



Resistivity n/p




Very lightly doped

n~, p--



Lightly doped

n- p-



Moderately doped

n, p



highly doped

n+, p+



Very highly doped



0.001 < 0.01/0.005

Figure 4.9 Silicon-on-insulator SOI (silicon/oxide/silicon) and SOS (silicon-on-sapphire) wafers

Further processing of the polished wafers leads to more specialized wafers. Epitaxy is a process for growing more silicon on top of a silicon wafer, with the doping level and/or the dopant type independent of the substrate wafer. Bonding of two (or even more) wafers together to create more complex wafers is another further development. Silicon-on-insulator (SOI) wafers can be made by, for example, wafer bonding (Figure 4.9). Silicon-on-sapphire (SOS) wafers rely on epitaxial deposition of silicon on top of a crystalline sapphire (Al2O3). It is also possible to create layers inside the wafer for additional functionality. These advanced wafers will be discussed in Chapters 15 (Ion implantation) and 17 (Bonding and layer transfer).


Even though silicon-wafer fabrication results in wafers with extremely well-defined properties, some defects are bound to be found. These defects can be classified according to their origin as grown-in defects and process-induced defects. The former are starting material and crystal-pulling related, and the latter result from the wafering process (at the wafer manufacturer) and from the wafer processing (in the wafer fab) (Table 4.6).

Metallic impurities come from polysilicon, quartz crucible, graphite and other hot parts of the growth system. The segregation coefficients of most metals are very small, and the crystal is purified relative to the melt. Metals are, however, fast diffusers in silicon, and they react with other defects and form clusters. Metals affect electronic devices by creating trapping centres in silicon midgap, reducing minority carrier lifetimes and lowering mobility. Metals can also precipitate at Si/SiO2 interface and reduce the oxide quality, as will be discussed in Chapter 24. The allowed iron level in silicon wafers is limited to 1010cm—3 (starting material limit) but at the end of an IC precess it

Table 4.6 Sources of non-idealities in silicon wafers

EGS polysilicon

Dopants (B, P) and other

impurities (C, metals)

Czochralski growth

Impurities from quartz

Oxygen from quartz

Carbon from graphite and SiC

Vacancies and interstitials



Wafering process

Contamination from tools

Mechanical distortions

Wafer processing


Crystallinity defects


Mechanical distortions


can be much higher because fabrication steps introduce more iron.

Point defects are zero-dimensional: vacancies (missing atoms in the lattice), substitutional impurities (foreign atoms at silicon lattice sites) and interstitials (atoms such as oxygen at non-lattice sites) (Figure 4.10). Diva-cancies and phosphorous-vacancy pairs are also pointlike defects. Point defects play an important role in diffusion, which is obvious because solid diffusion requires empty sites for atoms to move in the lattice. Some vacancies are present even at room temperature as a result of thermal equilibrium processes but additional vacancies generated by energetic or high temperature processing play a dominant role in diffusion.

One-dimensional or line defects are called dislocations. These come in many varieties, for example, extra half-planes inserted between the regular atomic planes. The order of magnitude of thermally generated stress a can be gauged by Equation (4.8):

where strain, e = aATa, depends on the silicon coefficient of thermal expansion, Young's modulus E (at i' i» !"

Figure 4.10 Schematic defects. (a) Foreign interstitial; (b) dislocation; (c) self-interstitial; (d) precipitate; (e) stacking fault (external); (f) foreign substitutional; (g) vacancy; (h) stacking fault (internal); (i) foreign substitutional. From Green, M.A. (1995), by permission of University of New South Wales

Figure 4.10 Schematic defects. (a) Foreign interstitial; (b) dislocation; (c) self-interstitial; (d) precipitate; (e) stacking fault (external); (f) foreign substitutional; (g) vacancy; (h) stacking fault (internal); (i) foreign substitutional. From Green, M.A. (1995), by permission of University of New South Wales the temperature in question) and AT, temperature difference. The silicon yield strength (a.k.a. critical shear stress) is strongly temperature dependent: at 850 °C it is ca. 50MPa, at 1000 °C only of the order of 10MPa, and ca. 1MPa at 1200 °C. Temperature differences between the wafer centre and the edge can easily lead to thermal stresses above the silicon yield strength. Stresses can be relaxed by slip-line formation.

Area defects include stacking faults, grain boundaries and twin boundaries. Processes that cause volume changes, such as oxidation, are prone to produce defects. Oxidation induced stacking faults (OISF) are a class of such defects.

Bulk defects include voids and precipitates. When the ingot is cooled down, the impurity and the dopant concentration exceed the solid solubility limit (see Figure 14.1 for solubility vs. temperature). Excess dopant or impurity will form precipitates. Oxygen precipitates (O2P) is one class of such volume defects. Oxygen, which is present in CZ-wafers at 5 to 20 ppma levels, is initially dissolved in interstitials sites, but can precipitate during thermal treatments. Precipitation can take place on the surface or in the bulk. Bulk precipitates act as gettering centres for impurities and are thus beneficial. Carbon atoms act as nucleation sites and centres for oxygen precipitation.

Microvoids are clusters of vacancies formed inside the ingot during crystal pulling. When wafers are cut and polished, these voids end up at wafer surface. A microvoid causes a laser scatterometry signal similar to a particle. Vacancy clusters were therefore classified as particles, and were given the name COP, for Crystal Originated Particles (today, advanced multiangle scatterometry tools can distinguish voids from particles). It was the fact that the number of COPs did not decrease in cleaning (and it could in fact increase!) that lead to a reassessment of their nature. Typical COP sizes are 50 to 200 nm, and they are found in concentrations of 104 to 106 cm-3.

Haze is defined as light scattering from surface defects, for example, scratches, surface roughness or crystal defects. Haze measurement is by done by scatterometry, and the whole wafer is scanned in haze measurement, in contrast to roughness measurement, which is local area measurement only, for instance, 5 x 5 ^m area by AFM.


1. Calculate an estimate for silicon lattice constant from atomic mass and density.

2. Consider an Olympic swimming pool filled with golf balls and one squash ball. If the golf balls represent silicon atoms, and the squash ball represents a phosphorous atom, what would be the resistivity of a silicon piece with such a doping concentration?

3. Electronic grade polysilicon is available with 0.01 ppb phosphorous concentration. What is the highest ingot resistivity that can be pulled from such a starting material?

4. If 50 kg of ultrapure polysilicon is loaded into a CZ-crystal puller, how much boron should be added if the target doping level of the ingot is 10 ohm-cm?

5. Axial dopant profile along a CZ-ingot can be calculated from

where C0 is the initial dopant concentration in the melt, X is the fraction solidified and k0 is the segregation coefficient. If the wafer-resistivity specifications are 5 to 10 ohm-cm (phosphorus), calculate the fraction of the ingot that yields wafers within this specification.

6. If the neck in a CZ-ingot is 2 mm in diameter, what is the maximum ingot size that can be pulled before the silicon yields catastrophically?

7. If the COP density in the ingot is 105 cm-3, what is the COP density on the wafer surface?


Borghesi, A. et al: Oxygen precipitation in silicon, J. Appl.

Fischer, A. et al: Slip-free processing of 300 mm silicon batch wafers, J. Appl. Phys., 87 (2000), 1543. Green, M.A.: Silicon Solar Cells, Centre for Photovoltaic

Devices and Systems, NSW, Sydney, 1995. Hull, R.: Properties of Crystalline Silicon, IEE Publishing, 1999.

Jenkins, T.: Semiconductor Science, Prentice Hall, 1995. Müssig, H.-J. et al: Can Si(113) wafers be an alternative to Si(001)? Microelectron. Eng., 56 (2001), 195.

Petersen, K.: Silicon as a mechanical material, Proc. IEEE, 70 (1982), 420. Reprinted in W. Trimmer (ed.): Micromechan-ics and MEMS, Classic and Seminal Papers to 1990, IEEE Press, 1997, 58-95.

Shimura, F. (ed.): Semiconductors and Semimetals: Oxygen in Silicon, Willardson, 1994.

Shimura, F.: Semiconductor Silicon Crystal Technology, Academic Press, 1997.

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