Matrix layer


Figure 7. Schematic presentation of a semiconductor-matrix composite film in which the nominal semiconductor layer thickness ds varies between 1 and 6 nm and the matrix layer thickness is dm = 20 ds.

Figure 8. Cross-section view of the spatial arrangement of CdSe nanoparticles in as-deposited three layer structures Si0x(40 nm)/ CdSe(2 nm)/SiOx (20 nm) at high (a) and low (b) magnification. The spatial distribution of the nanoparticles follows the surface morphology of the SiOx layer.

semiconductor-doped glasses and their thin film counterparts. This technique, if applicable, can be very useful, especially for semiconductors such as Se, which form nanocrystals of very different sizes in the standard procedure of crystal growth in a diffusion-controlled phase decomposition of oversaturated solid solution.

Size Distribution and Structure A deeper inspection of the buried CdSe nanoparticles by high-resolution electron microscopy have shown [199] that nanoparticle crystal lattice is randomly oriented. Occasionally, deviations from the spherical shape have been observed indicating the effect of particle interaction by coalescence. The average size of CdSe NCs was estimated from the (119) band in the X-ray diffraction patterns of samples with various nominal CdSe sublayer thicknesses employing Scherrer's Eq. (9) and the values obtained were close to the nominal thickness of deposited CdSe layers. On the other hand, HREM evaluation of the particle sizes yielded a mean diameter, which is more than twice greater than the nominal layer thickness of deposited CdSe. Keeping in mind the above discussed reason for this discrepancy (internal strains and deformations), a value of e ~ 49 • 10-3 has been determined for nanocrystals having dNC = 3.0 nm, which indicates that as it might be expected, the level of microstrains rises with decreasing NC size.

The changes upon annealing of the SiOx-CdSe samples at 670 K have been studied by a cross-section HRTEM [199, 204]. It has been observed that after annealing at 670 K, crystal lattice of the CdSe nanoparticles remains oriented randomly, but their sizes increase a little and the spherical appearance is improved. From the high-resolution imaging of lattice plane fringes and by comparison of the diffractograms of both images, it has been estimated that the crystallinity of the CdSe nanoparticles is improved upon annealing. Values of 0.12 and 0.15

have been obtained for y/dNC ratio in as-deposited and annealed SiOx (20 nm)/CdSe(1 nm)/SiOx (20 nm) structures, respectively, (where ^ is half the width at half the maximum of the size distribution). In annealed SiOx(40 nm)/CdSe(2 nm)/SiOx(20 nm), VdNC « 0.21. This nanocrystallite size distribution is compatible and even slightly narrower than those reported for CdS [205] and Ge [206] nanocrystals grown in SiO2 matrix during the annealing of thin films of CdS-doped silica and Si1-xOxGey, respectively.

One important observation from the HRTEM micrographs is the high density of planar lattice defects in both as-deposited and annealed films. These defects could be among the reasons for the great difference in the average nano-crystal sizes obtained from the X-ray diffraction patterns and those seen in HRTEM micrographs. This raises the question for the lattice type present in the nanoparticles. Usually, CdSe is described by the hexagonal wurtzite B4 type, which was found also for CdSe nanoparticles from HRTEM studies [207, 208]. On the other hand, it is known that in the nanoscale range II-VI, semiconductors tend to change rather easily from the wurtzite to the cubic zincblende B3 type and vice versa [209, 210]. This transition and the corresponding stacking disorder have been rated by measuring the lattice fringe spacings of a number of particles [204]. It has been observed that in as-prepared samples (deposited at room substrate temperature), CdSe particles display a predominantly wurtzite lattice type, while in the annealed structures (at 670 K), CdSe particles of the sphalerite lattice type have been frequently seen. For the as-deposited nano-particle layer, three-quarters of the particles reveal spacings of the hexagonal and one-quarter spacings of the cubic or both lattice types. For the annealed structures, however, it has been found that approximately one-half of the particles reveal spacings of the cubic and another half spacings of the hexagonal or both lattice types, respectively. It is important to notice that in three-dimensional CdSe films deposited, the situation is just the opposite. The films deposited at low substrate temperatures (T < 370 K) show predominantly sphalerite structure. The annealing of three-dimensional films at 670 K converts their structure to wurtzite type. This difference in the behavior of three-dimensional and zero-dimensional CdSe is most likely due to surface-induced changes in bond strength in the nanoparticles.

Mechanism of Semiconductor Nanoparticle Formation

As discussed in Section 2, at the first stage of thin film deposition, the formation of embryos takes place, which depends on the temperature, chemical nature, structure, and clearness of the substrate surface [202]. In particular, the presence of steps on the substrate surface induces an increase in the embryo concentration at these steps. It has also been shown [211] that the curvature and stress at a rough or even disordered surface, strongly affect reaction rates at solid interface as they create different environments at different reaction sites. The sequential vapor deposition of two materials, which have been used for preparation of CdSe nanocluster layers, has been also applied for nonepi-taxial growth of nano-sized metallic clusters embedded in insulating matrix. Several assumptions have been previously mentioned for the mechanism of the metal nanoparticle formation. It has been assumed [186] that the existing valleys of the thin film a-Si:H surface support clustering of Mo and W. Also, the cluster formation at most of the transition and noble metals on insulator has been attributed [196] to the large difference of surface energies. The partial wetting character of Ga with respect to SiOx has been considered [190] as responsible for the formation of liquid Ga nano-clusters on the "smooth" surface of SiOx ultra-thin films. The cross-sectional electron micrograph of SiOx/CdSe multilayers have shown [95, 96] that when in the SiOx/Ga MLs the ultra-thin metal layers are replaced by CdSe semiconductor layers, the latter is continuous rather than "island" type. However, when the SiOx (GeS2, ZnSe) surface is "rough," CdSe particle formation takes place, as the spatial distribution of nanoparticles follows the surface morphology of the SiOx (GeS2) films. This implies that different mechanisms should be responsible for the metal and semiconductor nanoparticle formation. Obviously, the assumption for difference of surface energies cannot explain deposition of continuous CdSe layers on a relatively "smooth" surface and discontinuous ones on a relatively "rough" surface. In addition, one could not expect the same partial wetting character of CdSe with respect to SiOx, GeS2, and ZnSe.

The HRTEM and X-ray diffraction results showed that the surface roughness of SiOx layers in the SiOx/CdSe MLs having layer thicknesses <10 nm is relatively small. Therefore, it has been assumed [95] that a homogeneous embryo formation takes place at the first stage of CdSe deposition on the "smooth" SiOx surface. A gradual increase of the nanoparticle size and coalescence as well as new embryo formation can be expected further; CdSe layers become continuous at a nominal thickness >2.5 nm. The observed spatial distribution of the CdSe NCs in the composite films indicates that surface roughness plays an important role in the CdSe nanoparticle formation. It has been suggested [199] that at the very beginning of CdSe deposition on a "rough" oxide or chalcogenide surface embryos were formed at those surface positions at which the curvature and lattice stress are the greatest. The relatively narrow size distribution implies that further CdSe deposition does not create new embryos but leads mainly to an increase of the nanoparticle size. As the positions with great surface curvature and lattice stress are disposed accidentally, some embryos are created rather closely and, for this reason, some nanoclusters are in contact.

In the end of this section, we would like to pay attention to several slightly different applications of the multilayer approach. The first one is a size-controlled nc-Si synthesis, which has been recently realized in SiO/SiO2 MLs [212, 213]. Thermally induced phase separation has been applied in order to grow Si NCs in the SiO layers. By this technique, a separate control of crystallite size and density is possible. This approach allows fabrication of Si nanocrystals of a well-defined size and rather high density, which is very important for fabrication of light-emitting devices. Germanium island (6-7 nm in diameter) formation with a high density (2 x 1012 cm-2) has been reported [214] on ultra-thin SiO2 films. It is important that each dot in this multilayer structure had a boundary with the SiO2 film and, also, with a Si spacer layer.

Another application of the multilayer approach is in preparation of metal-doped films using metal dissolution

Table 3. Multilayers with discontinuous metal or semiconductor layers.

Discontinuous layer/matrix

Preparation technique

Table 3. Multilayers with discontinuous metal or semiconductor layers.

Discontinuous layer/matrix

Preparation technique


radio frequency sputtering [193-195]


thermal evaporation [190]


radio frequency sputtering [186]


radio frequency sputtering [186]


thermal evaporation of V, glow discharge

a-Si:H [186]




thermal evaporation [97, 98, 188, 199, 201]


thermal evaporation [97, 98, 200, 201]


thermal evaporation [97, 98, 201]


hot-wire CVD [202]


hot-wire CVD [202]


laser beam evaporation [203]


thermal evaporation, high temperature

annealing [213, 214]

in ammealed MLs [215]. Multilayers have been prepared by alternative metal (Ag) and chalcogenide (As33S67) vapor deposition in vacuum. Such MLs have shown a greater sensibility to illumination and a larger photo-dissolution rate in comparison to the conventional double-layer structure Ag/As33S67. The ML structure has been used to fabricate a phase grating for operation in the infrared region. Furthermore, Mo/Si MLs deposited using electron beam evaporation were used to study the formation of silicides at high temperatures [216]. It has also been demonstrated [217] that the introduction of SiO2 layers in the interface of Mo/Si multilayers was quite effective in improving the heat stability of the MLs. An asymmetric SiO2 layer thickness of 0.5 and 1.5 nm has been found to be most favorable at the Si-on-Mo interface an Mo-on-Si interface, respectively.

All multilayers described in Section 4, which contain discontinuous metal or semiconductor nanoparticle layers as well as techniques used for their preparation, are listed in Table 3.

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